1. Field of the Invention
The invention relates to an electrical communications system with storage of signals in general and more specifically an integrated circuit data processor implemented using a plurality of integrated circuit chips.
2. Description of the Prior Art
With the advent of large scale integration LSI, the number of logic gates which can be manufactured on a single integrated circuit chip has increased astronomically, while the ability to make external connections to carry signals to and from each chip has remained relatively constant.
Therefore in order to implement systems using LSI, the system must be organized or partitioned in such a fashion that the largest number of circuits on each chip can be utilized with the smallest number of signal input output connections to the chip.
The problems in system organization created by LSI circuitry are well recognized by many persons skilled in the art, an example being the publication by Abdul-Razzaq Habayeb entitled "System Decomposition, Partitioning and Integration For Microelectronics" which appeared in IEEE Transaction on Systems Science and Cybernetics, Vol. 4, No. 2, July 1968 at pages 164-172.
U.S. Pat. No. 3,462,742 is an example of a prior art system organization.
When the number of logic circuits on a chip is increased by an order of magnitude over the density contemplated in U.S. Pat. No. 3,462,742, a lesser number of chips is required to implement a data processor if each circuit on the denser chips can be efficiently utilized. The system organization of U.S. Pat. No. 3,462,742, however, does not lend itself to efficient utilization of circuits when a data processor is implemented using only two or three LSI circuit chips because this patents teachings require a master control unit.
Another prior art system organization which superficially appears similar to that of the instant invention is described in U.S. Pat. No. 3,537,074. The system of this patent includes a plurality of processors performing the same function upon different data in response to the same instruction. The system organization of this patent is especially valuable when the data to be processed is in the form of matrices or arrays and the same functional operation is to be performed on each element of the array such as a Fast Fourier transformation. Again a master control element 27 is required even though each processor performs an identical function.
Another system organization which is superficially similar to that of the instant invention is the classical multiprocessor organization, an example of which appears in U.S. Pat. No. 3,470,540. Classical multiprocessor system organization differs from the instant invention, however, in that in a multiprocessing system, each processor is performing a different functional operation upon different data in response to different instructions. A special form of the classical multiprocessing system organization is often called pipe line processing wherein a plurality of processors each operate on the results from a previous processor under control of commands from a common control unit. The pipe line processor system organization is also advantageous for array type data processing such as Fast Fourier transformation but is best implemented using a larger number of integrated circuits controlled by a master control unit or timing generator 15 such as described in U.S. Pat. No. 3,176,843.
All of the above recited prior art teachings require master or central control circuitry which must be connected to each integrated circuit chip by input output signal paths.